Can be isolated from the output of the programmable controller, the a/b/c contact relay, SSR, Tr output.Cable length: 3.0m.
Weight: 0.45kg.
Definition 1: conductor by one or a plurality of mutually insulated and insulating protective layer made of,
A conductor of electricity or information from one place to another MITSUBISHI FA-TB32XYL.
Definition 2: usually by a few or several groups (each with at least two wires) cable rope twisted the similar,
Each group of wires are insulated from each other, and are often twisted around a center,
The entire outer bread has a highly insulated cover FA-TB32XYL
The cable has the characteristics of internal power and external insulation. Convert connectors to fast connectors.
According to the location of the connection equipment distribution module MITSUBISHI FA-TB32XYL. Error output.
Rated open and close voltage, current: DC24V, 0.5A.
Minimum open and close load: DC5V, 1mA.
Response time (OFF, ON): 10ms below.
Response time (ON, OFF): 12ms below.
Life (Mechanical): more than 20 million times.
Life (Electrical) rated open and close voltage, current more than 100 thousand times.
Suitable for wire specifications: 0 MITSUBISHI FA-TB32XYL. 3 ~ 2 square mm (AWG22 ~ 14) (twisted pair / single line).
External wiring connection mode: spring clip terminal.
DC5V internal consumption current: 0.06A.
Weight: 0.11kg. Can be used as a screw relay terminal.Input and output (DC/ differential) MITSUBISHI Conversion module.
Input points: 12 points (DC5V/DC24V/ differential universal).
Pulse input speed: the highest pulse/s 8M (2MHz).
Output points: 8 points (DC5V ~ DC24V) 6 points (differential) MITSUBISHI Conversion module.
Pulse output speed: the highest pulse/s 8M (2MHz).
High speed and stable input / output response
The high speed response can be achieved without the CPU module''s operation and bus performance,
Stable input and output response through hardware processing MITSUBISHI Conversion module.
LD40PD01 is equipped with an external input and output interface and FPGA,
Therefore, high speed control can be realized without the influence of the scanning time of the CPU module and the bus performance (the input and output response time of the s instruction is realized).
Can achieve stable input and output response (processing time of the deviation of the ns level) FA-TB32XYL.
Through the intuitive tools for FPGA settings.
In the FPGA design process can be omitted in the past must be designed to deal with (HDL description, logic synthesis and time verification),
Reeduce working hours MITSUBISHI FA-TB32XYL. After receiving the product can be used immediately to verify the use of special tools, can significantly shorten the design time.